The present invention relates in general to a pulse width modulation (PWM) power converter, and more particularly, to a pulse width modulation power converter using zero voltage switching technique and power saving means.
Power converters have been frequently used to convert an unregulated power source into a constant voltage source. Transformers having a primary winding and a secondary winding are the hearts of most power converters. Typically a switching device is connected to the primary winding to control energy transferred from the primary winding to the second winding and output therefrom. Currently, under the control of the switching device, the pulse width modulation power converter can be operated at a constant high frequency with reduced size and weight. However, such a power converter suffers from the issues of switching loss, component stress and noise, and electromagnetic interference (EMI).
To resolve the switching loss problem of the pulse width modulation power converters, a phase-shift scheme for soft switching operation has been proposed, particularly for the high-frequency power conversion. For example, the full-bridge (FB) quasi-resonant zero-voltage switching (ZVS) technique has been disclosed in U.S. Pat. No. 4,855,888, xe2x80x9cConstant frequency resonant power converter with zero-voltage switchingxe2x80x9d, issued to Christopher P. Henze, Ned Mohan and John G. Hayes at Aug. 8, 1989, U.S. Pat. No. 5,442,540, xe2x80x9cSoft-switching PWM convertersxe2x80x9d issued to Guichao C Hua and Fred C. Lee at Aug. 15, 1995, and xe2x80x9cSoft-switched full-bridge convertersxe2x80x9d disclosed by Yungtaek Jang and Milan M. Jovanovic at Mar. 12, 2002. In U.S. Pat. No. 5,973,939, xe2x80x9cDouble forward converter with soft-PWM switchingxe2x80x9d issued to F. Don Tan at Oct. 26, 1999 and U.S. Pat. No. 6,191,960, xe2x80x9cActive clamp isolated power converter and method of operating thereofxe2x80x9d issued to Simon Fraidlin and Anatoliy Polikarpov at Feb. 20, 2001, the active clamp technique has been employed in the forward zero-voltage switching power converters. In U.S. Pat. No. 6,069,798, xe2x80x9cAsymmetrical power converter and method of operation thereofxe2x80x9d issued to Rui Liu at May 30, 2000, an asymmetrical scheme has been developed for a half-bridge (HB) topology.
Among various zero-voltage switching power converters, a parasitic leakage inductor of the transformer or at least one additional magnetic component is used as a resonant inductor or switch to generate a circulating current, so as to achieve the zero-voltage transition and switching operation. The parasitic leakage inductor of the transformer or the additional magnetic component, though providing the aid of zero-voltage transition and switching, consequently increases switching stress and noise.
Further, in such an approach, power consumption caused by circulating current is significantly high in the light load or zero-load condition.
The present invention provides a zero-voltage switching pulse width modulation power converter for high frequency operation. The zero-voltage switching pulse width modulated power converter is operated at a constant high frequency with low switching loss, low stress, and low noise.
The present invention further provides a zero-voltage switching pulse width modulation power converter that can realize a zero-voltage transition and switching operation without using an additional magnetic device or leakage inductor of the transformer.
The present invention also provides a zero-voltage switching pulse width modulation power converter that consumes relatively low power in the light load and zero-load conditions.
Further, the present invention provides a control scheme to optimize soft switching of a power converter.
The zero-voltage switching pulse width modulation power converter provided by the present invention comprises a transformer, a primary circuit, and a secondary circuit. The transformer has a primary winding coupled to the primary circuit and a secondary winding coupled to the secondary circuit. The zero-voltage switching pulse width modulation further comprises a feedback circuit, coupled to an output of the secondary circuit to generate a feedback voltage. The primary circuit further comprises a controller coupled to the feedback voltage. The controller is operative to conduct the primary winding to an input voltage source in response to the feedback circuit. In addition, the primary circuit further comprises a pair of main switches and a pair of auxiliary switches.
The soft-switching power converter further comprises a timing resistor coupled to the controller to adjust a pulse width of the second switching signal, a programming resistor coupled to the controller to determine a pulse width of the second switching signal as a function of a load of the power converter, and the controller may further comprise a reference resistor to determine a switching frequency of the power converter.
The controller is operative to generate the first and the second switching signals, such that each switching cycle of the power converter comprises four operation stages. In the first operation stage, the controller conducts the input voltage source and the primary winding via the main switches by generating the first switching signal. In the second operation stage, the controller switches off the first switching signal. In the third operation stage, the controller generates a second switching signal to conduct the input voltage source to the primary winding via the auxiliary switches. In the fourth operation stage, the second switching signal is switched off.
The present invention further provides a controller comprising an oscillator, an inverter, first to second comparators, first to third D-type flip-flops, and a first AND gate and a second AND gate. The oscillator is operative to generate a clock signal, a ramp signal and a saw signal. The inverter has an input terminal receiving the clock signal and an output terminal. The first comparator has a positive terminal connected to a feedback voltage obtained from an output voltage of the power converter, a negative terminal coupled to the ramp signal, and an output terminal. The second comparator has a positive terminal coupled to a variable current, a negative coupled to the saw signal, and an output terminal. A variable current flows through the timing resistor form the variable voltage that compares with the saw signal to produce a signal for generating the second switching signal. The first D-type flip-flop is coupled to the output terminals of the inverter and the first comparator and a voltage source. The first D-type flip-flop further comprises an output. The second D-type flip-flop is coupled to the output terminals of the inverter and the second comparator and the voltage source, and the second D-type flip-flip further comprises an output. The third D-type flip-flop is coupled to the output terminal of the inverter, and the third D-type flip-flop has a first output and a second output inverted from the first output. The first output of the third D-type flip-flop output a first enable signal for the first switching signal. The second output of the third D-type flip-flop output a second enable signal for the second switching signal. The first AND gate is coupled to the outputs of the first D-type flip-flop and the inverter, and the first enable signal. The second AND gate is coupled to the outputs of the second D-type flip-flop and the inverter, and the second enable signal. The first AND gate generates a first switching signal to drive the main switches, and the second AND gate generates the second switching signal to drive the auxiliary switches.
The controller further comprises a variable current source to generate the variable current. The variable current source comprises a programmable current, an I/V resistor, an op-amplifier, a constant current source, a pair of mirrored transistors and a transistor. The programmable current flowing through the I/V resistor generates a voltage that is connected to the positive input terminal of the op-amplifier. The negative input terminal of the op-amplifier is connected to the transistor and the programming resistor, wherein the programming resistor determines a pulse width of the second switching signal as a function of a load of the power converter. The pair of mirrored transistors is connected to the constant current source. The transistor is coupled to one of the mirrored transistors. Another mirrored transistor outputs the variable current.
The oscillator comprises a reference voltage, a mirrored transistor, a transistor and an op-amplifier to generate a reference current through the reference resistor.
The op-amplifier is coupled between the reference voltage, the transistor and the resistor. The transistor is coupled to one of the mirrored transistor to generate the reference current.
The oscillator further comprises three mirrored transistors, a transistor, a first and second op-amplifiers, a resistor and a constant current source mirrored from the reference current. Three mirrored transistors are connected to the constant current source. The transistor is coupled to the first mirrored transistor. The first op-amplifier is coupled between the transistor and the feedback voltage. The resistor is coupled to the transistor and the first op-amplifier. The second op-amplifier is coupled to the resistor and a threshold voltage. The second mirrored transistor outputs the programmable current. The third mirrored transistor outputs a programmable discharge current. The programmable current and the programmable discharge current are proportional to a mirror ratio of the mirrored transistors and the difference between the feedback voltage and the threshold voltage, and inversely proportional to resistance of the resistor. Due to the feedback voltage is decreased in response to the decrease of the output load of the power converter, therefore the programmable current and the programmable discharge current are reduced in light load and no load conditions.
The oscillator further comprises a frequency capacitor, operative to determine operation frequency. The reference current mirrors a charge current that associates with the frequency capacitor generate the ramp signal and determine the maximum on-time of the first switching signal. The oscillator further comprises first-pair of mirrored transistor and second-pair of mirrored transistor, a first-disable transistor and second-disable transistor for the control of discharge current. The reference current further mirrors a discharge current that flows through the second-pair of mirrored transistor to discharge the frequency capacitor, wherein the discharge current is enabled by a second discharge signal via the second-disable transistor. The discharge current associates with the frequency capacitor determine the off-time of the second switching signal. The programmable discharge current that flows through the first-pair of mirrored transistor to discharge the frequency capacitor, wherein the programmable discharge current is enabled by a first discharge signal via the first-disable transistor. The programmable discharge current associates with the frequency capacitor determine the off-time of the first switching signal. Since the programmable discharge current is reduced in accordance with the decrease of the load in light load condition, the off-time of the first switching signal is increased accordantly. In the meantime the off-time of the second switching signal is keep as a constant, which maintains a short delay time for achieves the zero voltage transition before the start of next switching cycle. Consequently, the off-time of the first switching signal is increased, the switching frequency of the switching signal is decreased and thus the switching losses and the power consumption of the power converter is reduced in light load and no load conditions.
The oscillator further comprises three comparators, four NAND gates, a NOR gate, a transistor, a current source, a switch, a capacitor, and a release current that is mirrored by the reference current. The negative input terminal of first comparator and the positive input terminal of second comparator are connected to the frequency capacitor. In order to determine the switching frequency and the ramp signal, the positive input terminal of first comparator and the negative input terminal of second comparator are connected to a high threshold voltage and low threshold voltage respectively. The first and second NAND gates form a S-R latch circuit. The input of the first and second NAND gate is connected to the output of the first and second comparator respectively. The first NAND gate outputs a clock signal that is connected to the input of third and fourth NAND gates. The first and second enable signal applied to the third and fourth NAND gates to generate the first discharge signal and the second discharge signal for the off-time control of the first and second switching signal. The clock signal is also applied to turn on the switch, which associates with the release current and the capacitor produce the saw signal. Accordantly, the saw signal is used to compare with the variable voltage to generate the signal for the second switching signal. The positive input terminal of the third comparator is connected to the current source and the detection diode for the detection of zero voltage transition. The current source is used for pull-high. The negative input terminal of the third comparator is coupled to a threshold voltage. Once a low signal is detected by the third comparator, during the period of second switching signal, the transistor will be turned on by the NOR gate to rapidly discharges the frequency capacitor and starts the next switching cycle in time. Therefore the zero voltage switching is achieved and the efficiency of the power converter is improved.
Advantageously, the zero-voltage switching PWM power converter of the invention is operated at a constant high frequency with low switching loss, low stress, and low noise. The zero-voltage switching PWM power converter can realize a zero-voltage transition and switching operation without using an additional magnetic device or leakage inductor of the transformer. It consumes relatively low power in the light load and zero-load conditions.